The present invention relates to a semiconductor memory and, more particularly, to a circuit technology suited for driving the BIT lines of the memory at a high speed and reducing the power consumption of the memory, particularly with high integration.
It is essential in order to achieve a high-speed operation of a bipolar memory to discharge at high speed. BIT lines having heavy load. The prior art has coped with this by increasing the readout current that functions as the BIT line discharge current. One example of the prior art is shown in FIG. 2. In the figure, the reference symbol C denotes a memory cell, W, LW word lines, B0, B1 BIT lines, Q0, Q1 reference transistors, BS a BIT line select signal, BD a BIT line drive circuit having npn transistors Q2-Q6 and resistor R3, IB0, IB1 BIT line discharge current sources, I y BIT line drive circuit current source, OB an output buffer, and D0 a data output signal. In the memory cell C, a readout current of several mA is allowed to flow by connecting a resistor R to cross coupled transistors Q0 and Q1 in series to a Schottky barrier diode SBD, as described in Japanese Patent Publication No. 62-7639. Thus, the load capacitance of the BIT lines can be discharged at high speed.
In recent years, a number of circuits using both insulated gate type transistors and bipolar transistors have been proposed for making the high integration and speed of the memory compatible. In the circuit disclosed in Japanese Patent Publication No. 63-31879, published May 21, 1981 as Laid Open Patent No. 56-58193 the memory cell is composed of the insulated gate type transistors suitable for the high integration, and the selection circuit, the read/write control circuit, the sense amplifier and so on are composed of the bipolar transistors suitable for the high speed. Thus, the disclosed circuit can realize both the high integration and speed remarkably efficiently. In this example, moreover, the voltage amplitude of the BIT lines for reading out the information by switching the word lines is reduced to a remarkably small value (e.g., about 70 mV) so that a high-speed reading can be achieved. With the remaining large values in the BIT line amplitude (e.g., about 0.2 V) when the information is to be read out by switching the BIT lines and in the BIT line amplitude (e.g., 3.2 V) when the information is to be written in, however, the speed-up is limited when the information is to be read out or written in by switching the BIT lines. Since, moreover the cell current flows to all the cells connected with the selected word lines, there is also a limit to the reduction in the power consumption.
The aforementioned example of the prior art is shown in FIG. 17, a circuit diagram showing the memory cell and peripheral circuit of a semiconductor memory. In FIG. 17: reference characters MC11 to MC22 designate memory cells; characters W1 and W2 designate word lines; characters BL1, BR1, BL2 and BR2 designate BIT lines; characters VYIN1 and VYIN2 designate BIT line selection signals fed to the BIT line driver BD1; and characters VRL and VRR designate read/write control signals. The parenthesized values indicate one example of the voltage values of the signals, for example the BIT line selection signal VYIN (0 V, 4.2 V) has a selected level of O V and a unselected level of 4.2 V, and the read/write control signals VRL and VRR (4 V, 0 V) have a read level of 4 V and a write level of 0 V.
In FIG. 17, when the memory cell MC11 is selected to read out the information, the word line W1 is driven to a high potential to turn on transistors QTL and QTR. The BIT line selection signal VYIN1 is driven to the selection level of 0 V to turn off transistors QYL and QYR, and the read control signals VRL and VRR are driven to the level of 4 V to turn on transistors QRL and QRR. If a transistor QNL in the cell MC 11 is now ON and QNR OFF, the cell current I.sub.cell flows from a sense amplifier SA to VEE through transistors QRL, QTL and QNL. In the unselected BIT line BL2, on the other hand, the BIT line selection signal VYIN2 is at the unselected level of 4.2 V and higher by 0.2 V than VRL and VRR (at 4 V), so that the cell current I.sub.cell flowing through the cell MC12 does not flow from the sense amplifier SA to VEE, but through the QYL or QYR in a BIT line driver BD2, through the QTL or QTR, and through QNL or QNR in the cell MC12. As a result, what flows through the sense amplifier SA is the cell current I.sub.cell of the cell MC11, which can be detected to read out the information of the cell MC11. It should be noted here that the potential of the selected BIT lines BL1 and BR1 is clamped at about 3.2 (=4-0.8) V if the base-emitter voltage of the transistors QRL and QRR is set at 0.8 V. As a result, when the selected word lines are switched to read out the information of the cell MC12, the potentials at the BIT lines BL1 and BR1 are hardly changed. In other words, the time period required for charging and discharging a large parasitic capacity of the BIT lines is reduced substantially to zero so that the reading can be accomplished at a remarkably high speed.
A semiconductor memory is disclosed in ISSCC Digest of Technical Papers, pp. 212,213, Feb. 1986, "A 13ns/500 MW 64 Kb ECL RAM" or Japanese Patent Laid-Open No. 62-58487.
Most of the memory LSIs of the prior art contain address buffers, address decoders, memory cell arrays, sense circuits and output buffers, and they have similar circuit structures. For example, most of BiCMOS static memories have a structure shown in FIG. 36A, and most of the bipolar memories have a structure shown in FIG. 36C.
As shown in FIG. 36A, address signals AX0 and AX.sub.1 are fed to an address buffer XB so that AX.sub.0 and AX.sub.0 ' (and AX.sub.1, and AX.sub.1 ') signals are outputted. Incidentally, this example has two inputs, but it is quite natural that the number of inputs is generally far larger. The aforementioned address buffer XB is frequently composed of bipolar transistors as its main components in case the address signals AX.sub.0 and AX.sub.1 are at the ECL (i.e., Emitter Coupled Logic) Level.
The output of the address buffer XB is decoded by a pre-decoder XD (which is composed of NAND gates, in this case). The output of the pre-decoder XD is fed to a decoder driver XDD so that one of the word lines is selected. In the structure of FIG. 36A, memory cells MC connected with a selected word line WL are all selected.
On the other hand, the selection in the column direction is accomplished by feeding a column selection signal YSS to a column selection circuit YS.
Thus, the information at the memory cell, which is located at the intersection of the selected row (i.e., word line) and the selected column (i.e., BIT line) is read out to the base of the current switch of a sense circuit SENS. This signal is amplified by the sense circuit SENS and fed to an output buffer (although not shown). For the writing operation, a common sense line CSL is set at a high or low level in accordance with the data to be written. After this, the column selection circuit YS is selected, or BIT lines DL and DL' are directly set to the high or low level. Here is omitted the circuit for this operation.
The memory cell MC is constructed of a flip-flop composed of two cross-coupled n-MOS transistors and two load resistors.